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| C8051F020 25 MIPS, 64 kB Flash, 12-Bit ADC, 100-Pin Mixed-Signal MCU Analog Peripherals 12-Bit ADC High-Speed 8051 C Core - - 1 LSB INL; no missing codes Programmable throughput up to 100 ksps 8 external inputs; programmable as single-ended or differential Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5 Data-dependent windowed interrupt generator Built-in temperature sensor (3 C) 1 LSB INL; no missing codes Programmable throughput up to 500 ksps 8 external inputs Programmable amplifier gain: 4, 2, 1, 0.5 Can synchronize outputs to timers for jitter-free waveform generation Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 25 MIPS throughput with 25 MHz system clock 22 vectored interrupt sources 4352 bytes data RAM 64 kB Flash; in-system programmable in 512-byte sectors (512 bytes are reserved) External parallel data memory interface 64 port I/O; all are 5 V tolerant Hardware SMBusTM (I2CTM compatible), SPITM, and two UART serial ports available concurrently Programmable 16-bit counter/timer array with 5 capture/compare modules 5 general-purpose 16-bit counter/timers Dedicated watchdog timer; bidirectional reset Real-time clock mode using Timer 3 or PCA Internal programmable oscillator: 2-16 MHz External oscillator: Crystal, RC, C, or Clock Can switch between clock sources on-the-fly Typical operating current: 10 mA at 25 MHz Multiple power saving sleep and shutdown modes Memory 8-Bit ADC Digital Peripherals Two 12-Bit DACs Two Comparators Internal Voltage Reference VDD Monitor/Brown-out Detector On-Chip JTAG Debug & Boundary Scan - On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) Provides breakpoints, single stepping, watchpoints, stack monitor Inspect/modify memory and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets IEEE1149.1 compliant boundary scan Clock Sources Supply Voltage: 2.7 to 3.6 V 100-Pin TQFP Temperature Range: -40 to +85 C VDD VDD VDD DGND DGND DGND AV+ AV+ AGND AGND TCK TMS TDI TDO RST Digital Power Analog Power JTAG Logic Boundary Scan Debug HW Reset 8 0 5 1 C o r e UART0 UART1 SMBus SPI Bus PCA P0 Drv P0.0 P0.7 SFR Bus 64 kB FLASH 256 Byte RAM 4 kB RAM External Data Memory Bus Timers 0, 1, 2, 4 Timer 3/ RTC P0, P1, P2, P3 Latches Crossbar Config. ADC 500 ksps (8-Bit) MONEN VDD Monitor External Oscillator Circuit Internal Oscillator WDT C R O S S B A R P1 Drv P1.0/AIN1.0 P1.7/AIN1.7 P2 Drv P2.0 P2.7 P3 Drv P3.0 P3.7 XTAL1 XTAL2 System Clock VREF1 Prog Gain VREF VREFD DAC1 VREF DAC1 (12-Bit) DAC0 (12-Bit) A M U X 8:1 P4.0 Bus Control DAC0 VREF0 AIN0.0 AIN0.1 AIN0.2 AIN0.3 AIN0.4 AIN0.5 AIN0.6 AIN0.7 CP0+ CP0CP1+ CP1- C T L P4 Latch P4 DRV P4.4 P4.5/ALE P4.6/RD P4.7/WR P5.0/A0 P5.7/A7 P6.0/A8 P6.7/A15 A M U X Prog Gain ADC 100 ksps (12-Bit) Address Bus A d d r D a t a P5 Latch P6 Latch P5 DRV P6 DRV TEMP SENSOR Data Bus P7 Latch CP0 P7 DRV P7.0/D0 P7.7/D7 CP1 Precision Mixed Signal Copyright (c) 2004 by Silicon Laboratories 6.15.2004 C8051F020 25 MIPS, 64 kB Flash, 12-Bit ADC, 100-Pin Mixed-Signal MCU Selected Electrical Specifications (TA = -40 to +85 C, VDD = 2.7 V unless otherwise specified) PARAMETER CONDITIONS GLOBAL CHARACTERISTICS Digital Supply Voltage Digital Supply Current Clock = 25 MHz with CPU active Clock = 1 MHz (VDD = 2.7 V) Clock = 32 kHz; VDD Monitor Disabled Digital Supply Current Oscillator not running; VDD Monitor (shutdown) Enabled Oscillator not running; VDD Monitor Disabled CPU & DIGITAL I/O PORTS Clock Frequency Range Port Output High Voltage IOH = -3 mA, Port I/O push-pull Port Output Low Voltage IOL = 8.5 mA Input High Voltage Input Low Voltage A/D CONVERTER Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Signal-to-Noise Plus Distortion Throughput Rate Input Voltage Range D/A CONVERTERS Resolution Differential Nonlinearity Guaranteed Monotonic Output Settling Time COMPARATORS Supply Current (each Comparator, VDD = 2.7 V) Response Time | (CP+) - (CP-) | = 100 mV Input Voltage Range Input Bias Current Input Offset Voltage MIN 2.7 10 0.4 20 10 0.1 DC VDD - 0.7 0.7 x VDD 0.3 x VDD 12 1 1 66 0 12 1 10 1.3 4 -0.25 -5 -10 0.001 VDD + 0.25 +5 +10 100 VREF 25 0.6 TYP MAX 3.6 UNITS V mA mA A A A MHz V V V V bits LSB LSB dB ksps V bits LSB s A s V nA mV Package Information D D1 C8051F020DK Development Kit MIN NOM MAX (mm) (mm) (mm) A 1.20 0.15 A1 0.05 A2 0.95 1.00 1.05 b D E1 E 0.17 0.22 0.27 16.00 14.00 0.50 16.00 14.00 - D1 e E E1 100 PIN 1 DESIGNATOR 1 e A b A1 A2 Precision Mixed Signal Copyright (c) 2004 by Silicon Laboratories 6.15.2004 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders |
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